1. Field of the Invention
Embodiments of the invention relate to a gate driving circuit for a power semiconductor element, and, in particular, to a gate driving circuit implementing an overcurrent protection circuit and a short circuit protection circuit.
2. Description of the Related Art
An intelligent power module (hereinafter referred to as an “IPM”) is known as a semiconductor device used in a power conversion apparatus such as an inverter or a chopper. An IPM includes a plurality of semiconductor chips such as IGBT chips, and a driving circuit and a protection circuit therefor contained in a single package.
FIG. 9 is a circuit diagram of a conventional gate driving circuit 700 for an IGBT. The gate driving circuit is the part encircled by the dotted lines. A collector 1a of the IGBT 1 is connected to a main power supply not depicted in the figure. An emitter 1b of the IGBT 1 is connected to the GND, and a sense emitter is connected to the GND through a sense resistor 12. The symbol IE represents a main current running through the emitter 1b. The symbol VOS is a voltage generated at the time when a sense current Is flows through the sense resistor 12 to the GND, the sense current Is being proportional to and smaller than the main current Ic. The collector current Ic is divided into the emitter circuit IE and the sense current Is. The symbol VG represents a gate voltage of the IGBT 1.
An overcurrent detection circuit 4 is a comparator that compares the voltage VOS with an overcurrent protection threshold value VOC. The overcurrent detection circuit 4 outputs a signal when the voltage VOS exceeds the overcurrent protection threshold value VOC.
A delay circuit 5 is provided for the purpose of avoiding an undesirable effect of momentary operation of the overcurrent detection circuit 4 due to a noise or the like. The delay circuit 5 operates receiving an output from the overcurrent detection circuit 4 and delivers an output signal after a predetermined delay time. The output signal from the delay circuit is continuously delivered until the IGBT 1 completely becomes an OFF state. The output signal from the delay circuit 5 is inputted to a pre-driving circuit 11.
A MSOURCE 9, a p-channel MOSFET, has a gate 9c connected to the pre-driving circuit 11, a source 9b connected to a control power supply 14 (Vcc) for the gate driving circuit, and a drain 9a connected to a gate 1d of the IGBT 1. The MSOURCE 9, upon receiving an ON signal for the IGBT 1 from the pre-driving circuit 11, turns ON to make the IGBT 1 turn ON.
A MHOLD 10, an n-channel MOSFET, has a gate 10c connected to the predriving circuit 11, a source 10b connected to the GND, and a drain 10a connected to the gate 1d of the IGBT 1. The MHOLD 10, upon receiving an OFF signal for the IGBT 1 from the predriving circuit 11, turns ON to make the IGBT 1 turn OFF. At this moment, the MSOURCE 9 turns into an OFF state.
An OFF signal for the IGBT 1 is delivered in a normal OFF operation, in which any signal indicating an abnormality such as overcurrent does not exist. In addition, an OFF signal for the IGBT 1 is also delivered from the predriving circuit 11 when an abnormality such as overcurrent is detected by the overcurrent detection circuit 4 and an output signal is delivered from the delay circuit 5.
FIG. 10 shows operation waveforms in the gate driving circuit 700 shown in FIG. 9. When an output signal from the overcurrent detection circuit 4 is delivered through the delay circuit 5 to the predriving circuit 11 and an overcurrent state is identified, the MSOURCE 9 is turned OFF and the MHOLD 10 is turned ON. Electric charges accumulated on the gate 1d of the IGBT 1 are rapidly drawn out through the MHOLD 10 with a small ON resistance. As a result, the gate voltage VG rapidly decreases and the collector current IC rapidly decreases as well, causing hard interruption of the IGBT 1. The hard interruption of the IGBT 1 makes noises and thus, undesirable. A means for soft interruption of the IGBAT 1 is described in the following.
FIG. 11 is a circuit diagram of a conventional gate driving circuit 800 for soft interruption. The gate driving circuit 800 is different from the circuit of FIG. 9 in that a MSOFT 7, an n-channel MOSFET, is inserted between the gate 1d of the IGBT 1 and the GND. The ON resistance of the MSOFT 7 is selected to be larger than that of the MHOLD 10, which is an n-channel MOSFET. The output signal from the delay circuit 5 is delivered to the additionally provided MSOFT 7.
FIG. 12 shows operation waveforms in the gate driving circuit 800 of FIG. 11. Operation of the gate driving circuit 800 is described in the following with reference to FIG. 12. When a signal at the GND potential level is outputted from the predriving circuit 11, the MSOURCE 9 turns ON and a positive voltage is applied to the gate 1d of the IGBT 1. The IGBT 1 turns ON at the moment when the gate voltage VG reaches the gate threshold voltage VGtho. Upon turning ON of the IGBT 1, the collector circuit Ic starts to flow. The gate voltage VG becomes constant when the voltage VG reaches the gate threshold voltage VGtho. After certain period of the constant voltage, the gate voltage VG increases again until reaching the control power supply voltage Vcc and stays at that value thereafter. An emitter current IE flows through the emitter 1b of the IGBT 1 and a sense current Is flows through the sense emitter 1c. This sense current Is flows to the GND through the sense resistor 12. The voltage VOS arises in the sense resistor 12 with the sense current Is. The sense current Is is proportional to the collector current Ic and has a current magnitude in a range from 1/(several tens of thousands) to 1/(several hundred).
When the VOS reaches the VOC, the judgment is made that the emitter current IE have reached a level of overcurrent and an output signal is delivered from the overcurrent detection circuit 4 to the delay circuit 5 to operate the delay circuit 5.
After a predetermined period of time OCdelay from start of operation of the delay circuit 5, an output signal is outputted from the delay circuit 5. During the period to the time at which the output signal is outputted, the collector current IC continues to increase. When the output signal is outputted from the delay circuit 5, the MSOFT 7 turns ON. In the MSOFT 7, the total current flows consisting of a current from the high potential side 14 of the control power supply through the MSOURCE 9 and a current of charges being drawn out from the gate 1d of the IGBT 1 on which the charges have been accumulated. Since the ON resistance is large in the MSOFT 7, the gate voltage VG decreases slowly until reaching the VGtho. At the moment when the gate voltage VG reaches the VGtho, the collector current Ic turns to a decreasing process. Since the gate voltage VG decreases slowly, the collector current Ic also decreases slowly (soft interruption). Therefore, the oscillation superimposed on the waveform between collector and emitter is mitigated, suppressing noise generation.
Afterwards, the MHOLD 10 turns ON receiving a signal from the predriving circuit 11, thereby turning the IGBT 1 OFF completely.
Japanese Unexamined Patent Application Publication No. 2003-134797 (also referred to herein as “Patent Document 1”) discloses a gate driving circuit for avoiding generation of high surge voltage in the process of interruption of a power device upon detection of an abnormality. The circuit operates as described below. An OR circuit receives an output from an overcurrent detection circuit for detecting an overcurrent and an output from an abnormality detection circuit for detecting an overheating, an insufficient voltage, or the like. When an abnormality is detected in the overcurrent detection circuit or the abnormality detection circuit, two MOSFETs of a first MOSFET and a second MOSFET are controlled to decrease the gate voltage Vg of the IGBT. In this condition, a third MOSFET for ON control of the IGBT is changed to an interrupted state to interrupt the IGBT. After that, a fourth MOSFET for OFF control of the IGBT is changed to a conductive state. Owing to this means, the IGBT is softly interrupted not only in the event of overcurrent generation, but also on detection of any abnormality, and thus, surely avoiding generation of high surge voltage.
Japanese Unexamined Patent Application Publication No. 2001-314075, (also referred to herein as “Patent Document 2”) discloses a means for avoiding increase in turn off loss despite variation of component characteristics of power semiconductor elements. This means is described below. A comparator circuit detects that a gate-emitter voltage Vge of a power semiconductor element has reached a certain threshold value. The output from the comparator circuit and an output from a delay circuit are inputted to an AND circuit. The output from the AND circuit is delivered to a DFF (a D-type flip-flop). An output of a one-shot circuit for triggering rise up of the delay circuit is delivered to the clock side of the DFF. If the signal output time from the AND circuit is longer than a normal signal output time of the one-shot circuit due to variation of characteristics, the output from the DFF is set to be a high level to turn a fourth switch ON, thereby decreasing the gate resistance and attaining fast turn OFF operation.
Japanese Unexamined Patent Application Publication No. 2002-119044 (also referred to herein as “Patent Document 3”) discloses a means for avoiding increase in a turn off loss even in a high temperature condition by varying a resistance value of combined two resistances provided between a gate and emitter of the IGBT.
Japanese Unexamined Patent Application Publication No. 2008-118767 (also referred to herein as “Patent Document 4”) discloses a means for performing current limitation of an IGBT precisely and stably despite variation in characteristics of component elements. This means is described below. Emitter current of the IGBT is shunted and inputted to a comparator, which detects a sense voltage and compares the sense voltage is with a reference voltage Vref. If the sense voltage is larger than the reference voltage Vref, an MOSFET is turned ON by the comparator and charges at the gate of the IGBT are drawn out while making the sink side current I1 constant by a constant current source, thus limiting the main current of the IGBT.
The conventional gate driving circuit 800 shown in FIG. 11, however, needs a long time until turning to a decreasing process after judgment of overcurrent in the collector current Ic. Comparison between FIG. 10 and FIG. 12 demonstrates that the time period until turning to a decreasing process after judgment of overcurrent in the collector current Ic is longer in the gate driving circuit 800 of FIG. 11. A heavy overcurrent is flowing at the moment of interruption of the IGBT 1 in this example and overcurrent breakdown of the element often occurs. In the case of load short circuit or large gate capacitance of the IGBT in this construction, a long time is necessary to draw out the charges on the gate due to the effect of a mirror capacitance. During that period, over current or short circuit current continues to flow in the IGBT 1, resulting in breakdown of the element.
Patent Document 1, although discloses a means for avoiding generation of high surges (noises) by providing with a MSOFT (MOSFET 14) and a MSINK (MOSFET 15), does not mention about a means in which the gate voltage of the IGBT is monitored and the MSINK is separated to perform soft interruption of the IGBT.
In the circuits of Patent Documents 2 through 4, a gate potential monitoring circuit is provided for monitoring the gate voltage of the IGBT and, during continued ON state of the IGBT, the MOSFET (MSINK) for fast decreasing of the gate voltage is separated. And the MOSFET (MSOFT) is operated for slowly decreasing the gate voltage. Thus, soft interruption of the IGBT is performed and device breakdown due to overcurrent or short circuit is avoided. However, the documents are silent about a gate driving circuit for suppressing accompanied noise generation.